Electrically erasable programmable read only memory (EEPROM) are non volatile memory devices which use floating gate metal oxide semiconductor technology to store data. Each EEPROM cell contains a floating gate MOS transistor. A logical state is written into the EEPROM cell by providing a required voltage between the substrate, source, gate and drain of the floating gate MOS transistor in order to cause tunneling (Fowler-Nordheim tunnelling) of electrons from the substrate through the floating gate insulator (sometimes known as the tunnel oxide) onto the floating gate. The other logical state is written by providing specific voltages between the source, gate and drain which discharge electrons from the floating gate of the EEPROM cell by tunneling electrons through the floating gate insulator layer from the floating gate to the substrate.
FIGS. 1(a)-(d) are schematic cross-sectional diagrams illustrating the fabrication process of a typical prior art EEPROM cell. In FIG. 1(a), a shallow trench isolation (STI) structure 104 is formed within a silicon substrate using any suitable process known in the art. Each of the 2 parts of the STI structure 104 are separated by a substrate portion 102. A polysilicon (Poly 1) layer (not shown) that is disposed above the substrate portion 102 and STI structure 104 is completely etched. The Poly 1 layer is typically used to form the logic device poly gate, which is located at the logic circuit area. In FIG. 1(b), a tunnel oxide layer 106, usually comprising silicon dioxide, is grown on the substrate portion 102 and STI structure 104. In FIG. 1(c), a layer of polysilicon 108 is deposited above the tunnel oxide layer 106. In FIG. 1(d), the tunnel oxide layer 106 and polysilicon layer 108 are etched through suitable photolithography and etching processes. The layer of polysilicon 108 functions as a polysilicon floating gate (FG). The polysilicon floating gate 108 conforms to the topology of the underlying tunnel oxide layer 110, substrate portion 102 and STI structure 104. In FIG. 1(e), a dielectric layer 114 is deposited above the polysilicon floating gate 108. The dielectric layer 114 is typically made of a Oxide/Nitride/Oxide (ONO) sandwich and is deposited above the polysilicon floating gate 108 though any suitable process (e.g. low pressure chemical vapour deposition (LPCVD)). A control gate (CG) layer 116 is in turn deposited on the dielectric layer 114. The combined polysilicon floating gate 108, dielectric layer 114 and control gate layer 116 forms the EEPROM's capacitive structure. The capacitive structure is able to store charges and of the presence/absence of a charge determines the value (1 or 0) of the EEPROM cell.
In current EEPROM cells, especially those with a low couple ratio, due to the relatively smaller area of overlap between the floating gate and the control gate (resulting in a lower capacitance within the EEPROM cell) there is usually a need to generate a relatively high voltage to program the EEPROM cell. Herein, couple ratio is defined as the ratio of the capacitance of FG/CG to the total capacitance of the FG surrounding area. For simplicity, the couple ratio can be taken to be approximately equal to the capacitance of FG/CG to the sum of the FG/CG capacitance and the FG/Silicon substrate capacitance, as the remaining area contributes a relatively small portion of the capacitance due to relatively thick dielectric thickness (e.g. STI thickness>>Tunnel oxide or ONO dielectric oxide)
A need therefore exists to provide an EEPROM cell structure and a method of fabricating the same that seeks to address at least one of the above-mentioned problems.